Silicon etching is used to selectively remove material from silicon wafers during semiconductor, MEMS, sensor, photonics, and microfluidic fabrication. Common silicon wafer etching methods include wet chemical etching, dry plasma etching, anisotropic etching, isotropic etching, KOH and TMAH processing, and deep reactive ion etching (DRIE). UniversityWafer supplies silicon substrates in multiple orientations, thicknesses, diameters, and polish options for research and microfabrication applications.
UniversityWafer supplies silicon wafers for etching applications used in semiconductor fabrication, MEMS, microfluidics, sensors, photonics, anodic bonding, thermal devices, and university research. Available options include <100> and <111> silicon wafers, double-side polished (DSP) substrates, custom thicknesses, and wafers suitable for wet etching, dry etching, micromachining, and bonding applications.
Selecting the correct wafer before etching is important because crystal orientation, thickness, polish, flatness, resistivity, and surface condition can affect etch behavior, feature geometry, bonding performance, and final device results.
A university researcher requested silicon substrates for the fabrication of micro-planar heat pipes using silicon etching followed by anodic bonding to glass.
Research Request:
Double-side polished <100> silicon wafers with thicknesses between 1 mm and 2 mm for etching and anodic bonding to Borofloat® glass. Wafer diameters from 2 inch to 4 inch were acceptable, with quantities ranging from 1 to 5 wafers for prototype development and testing.
Reference #325439 for specifications and pricing.
For similar projects, UniversityWafer can supply double-side polished silicon wafers, custom thickness substrates, wafers for backside processing, and compatible Borofloat® glass substrates for anodic bonding and microfluidic device fabrication.
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Crystal orientation is especially important for anisotropic silicon etching. Wafers with <100> and <111> orientations can produce different etch geometries because crystallographic planes etch at different rates in chemistries such as KOH and TMAH.
For many MEMS and micromachining applications, <100> silicon wafers are commonly selected when predictable angled sidewalls, V-grooves, cavities, or diaphragms are required.
Wafer thickness can influence etch depth, mechanical strength, membrane formation, handling, and bonding requirements. UniversityWafer offers standard and custom thickness silicon wafers for applications ranging from shallow surface processing to deep cavities and thick micromachined structures.
Single-side polished and double-side polished silicon wafers are available depending on process requirements. DSP wafers are commonly selected for applications involving backside alignment, through-wafer processing, optical access, precision bonding, or fabrication on both wafer surfaces.
Wafer flatness, total thickness variation, surface roughness, and cleanliness can become important when etching is followed by photolithography, wafer bonding, thin-film deposition, or precision alignment.
Different chemicals are used for different materials during wafer processing. For bulk crystalline silicon etching, common anisotropic wet etchants include KOH and TMAH.
Choosing the correct chemistry depends on whether the process is intended to remove silicon, silicon dioxide, masking materials, or other deposited layers.
Many etched silicon devices are subsequently bonded to glass, silicon, or other substrates. Applications such as microfluidics, pressure sensors, MEMS packaging, and thermal devices may require carefully matched wafer thickness, flatness, surface finish, and cleanliness.
UniversityWafer supplies silicon substrates and compatible materials for processes such as anodic bonding, including Borofloat® glass and double-side polished silicon wafers.
Researchers use silicon wafers for etching projects involving:
If your project requires a specific wafer orientation, thickness, diameter, polish, resistivity, or bonding-compatible substrate, include those specifications in your quote request so the most appropriate silicon wafer can be matched to your process.
Silicon etching is the controlled removal of silicon from a wafer surface to form trenches, cavities, channels, membranes, vias, and other micro- or nanoscale structures. Silicon wafer etching is widely used in semiconductor manufacturing, MEMS, sensors, microfluidics, photonics, wafer bonding, and advanced research.
The appropriate etching process depends on the required feature geometry, etch depth, sidewall profile, surface finish, mask material, wafer orientation, and selectivity. Silicon etching methods are commonly classified as wet or dry and as anisotropic or isotropic.
| Method | Process Type | Typical Profile | Common Uses |
|---|---|---|---|
| KOH Etching | Wet, anisotropic | Crystal-plane dependent | V-grooves, cavities, MEMS, micromachining |
| TMAH Etching | Wet, anisotropic | Crystal-plane dependent | MEMS, diaphragms, sensors, silicon micromachining |
| Isotropic Wet Etching | Wet, isotropic | Rounded features and undercut | Surface shaping, cavities, specialized micromachining |
| Reactive Ion Etching (RIE) | Dry plasma etching | Controlled, directional features | Pattern transfer, microelectronics, MEMS |
| Deep Reactive Ion Etching (DRIE) | Dry plasma etching | Deep, high-aspect-ratio trenches | MEMS, through-silicon structures, advanced packaging |
Anisotropic silicon etching removes silicon at different rates depending on crystallographic orientation. This behavior makes it possible to create controlled geometries such as V-grooves, cavities, diaphragms, and other precision structures used in MEMS and microsystems.
Two widely used anisotropic wet etchants are potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). Their etch rates vary between silicon crystal planes, so wafer orientation is an important design parameter.
For example, <100> silicon wafers are commonly selected for anisotropic etching because the slower-etching {111} planes can define predictable angled sidewalls. <111> silicon wafers behave differently because of their crystallographic orientation and may be selected for specialized structures.
Isotropic silicon etching removes material in multiple directions at similar rates rather than following specific crystal planes. This can create rounded profiles and undercut beneath masking layers.
Isotropic etching may be useful when the objective is uniform material removal, rounded cavities, release structures, or surface shaping rather than crystal-plane-defined geometries.
Wet silicon etching uses liquid chemical solutions to remove exposed silicon. KOH and TMAH are commonly used for anisotropic etching of crystalline silicon and are especially important in MEMS and silicon micromachining.
Wet processes can offer relatively simple equipment requirements, high throughput, and strong selectivity depending on the substrate, masking layer, chemistry, temperature, and process conditions.
It is important to distinguish between chemicals used to etch silicon and chemicals used primarily to remove silicon dioxide (SiO₂). Hydrofluoric acid (HF) and buffered oxide etch (BOE), for example, are commonly used for oxide removal and surface preparation rather than as primary bulk crystalline silicon etchants.
Dry silicon etching uses plasma-based processes and reactive gases to remove material with a high degree of control. Dry etching is widely used when precise feature dimensions, directional etching, reduced undercut, or advanced pattern transfer are required.
Reactive ion etching (RIE) combines chemical reactions with ion bombardment to produce controlled material removal and directional profiles.
Deep Reactive Ion Etching (DRIE) is used to produce deep, high-aspect-ratio structures in silicon. A common implementation is the Bosch process, which alternates between etching and sidewall-passivation steps.
DRIE is especially useful for structures that require deep trenches, nearly vertical sidewalls, or substantial silicon removal while maintaining relatively narrow feature widths.
The starting wafer can significantly influence the etching process. Important specifications include crystal orientation, wafer thickness, resistivity, surface polish, flatness, and diameter.
UniversityWafer supplies silicon wafers for etching applications, including (100) oriented wafers, double-side polished silicon wafers, custom thickness substrates, and wafers for MEMS, microfluidics, anodic bonding, and semiconductor research.
The best silicon etching method depends on the required feature geometry, wafer orientation, target depth, process selectivity, masking system, and final device requirements.
