Custom Silicon Wafer Dicing Services
UniversityWafer provides precision
silicon wafer dicing services for research, prototype development,
semiconductor fabrication, MEMS, sensors, spectroscopy, and thin-film applications.
We can dice many substrate materials and wafer thicknesses into custom squares,
rectangles, dies, chips, or coupons according to your required dimensions and
tolerances.
Available options may include single-side polished or
double-side polished silicon wafers,
intrinsic or doped material, high-resistivity silicon, oxide-coated wafers,
custom crystal orientations, blue-tape mounting, wafer-cassette packaging, and
individual die handling.
Diced Undoped Silicon for Spectroscopy Research
A university Ph.D. researcher requested the following custom diced silicon wafers:
“I would like a quote for your low-cost diced
undoped silicon wafers
in 10 mm × 10 mm die sizes. The requested material is 525 µm thick,
single-side polished, <100> orientation, undoped, and greater than
10,000 ohm-cm.
The silicon dies will be used for
positron annihilation spectroscopy.
Please provide pricing for a quantity of 20 pieces.”
Please reference inquiry #270386 for specifications and pricing.
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Silicon Wafer Dicing and Clean Packaging
A senior research and development physicist asked about the handling,
dicing, storage, and shipment of
RCA-cleaned silicon wafers.
“We are evaluating the best way to store and ship RCA-cleaned wafers.
When you refer to sealed wafer cassettes, are the wafers vacuum sealed,
or could they still be exposed to moisture and airborne particles?
Is the wafer dicing process also performed in a controlled clean
environment?”
UniversityWafer quoted the following custom specification:
Item IS92b — Quantity: 4 wafers
-
Material: Float-zone intrinsic
undoped silicon
- Wafer diameter: 4 inches, 100.0 ± 0.5 mm
- Wafer thickness: 3,000 ± 25 µm
- Die dimensions: 21 mm × 21 mm
- Side-length tolerance: ±0.2 mm
- Crystal orientation: <100> ± 0.5°
- Resistivity: greater than 20,000 ohm-cm
- Minority-carrier lifetime: greater than 1,000 µs
-
Surface finish:
both sides polished
- Surface roughness: Ra less than 1 nm, process guarantee
- Edge configuration: one flat
- Estimated yield: approximately six squares per wafer
- Packaging: mounted on blue tape and sealed in individual wafer cassettes
Reference inquiry #23278 for specifications and pricing.
What Are Diced Silicon Wafers?
Silicon wafer dicing is the process of cutting a full
silicon wafer
into smaller individual pieces known as dies, chips, squares, or coupons. These
diced silicon wafers can be produced in custom dimensions for
semiconductor fabrication, MEMS devices, sensors, photonics, thin-film deposition,
materials testing, and university research.
UniversityWafer can provide custom die sizes from a wide range of substrates,
including prime-grade, test-grade, intrinsic, doped, oxidized, and
double-side polished silicon wafers.
Wafer diameter, thickness, crystal orientation, resistivity, surface finish, edge
tolerance, and packaging can be selected according to the application.
Silicon Wafer Dicing and Wafer Singulation
Wafer singulation separates a processed wafer into individual dies
after fabrication, coating, patterning, or device processing. The appropriate
wafer cutting method depends on the substrate material, wafer
thickness, required die dimensions, kerf width, edge quality, contamination limits,
and acceptable levels of mechanical or thermal stress.
Dicing can be performed on standard
silicon wafers,
thermal oxide wafers,
silicon-on-insulator wafers,
and other semiconductor or optical substrates. The selected method should minimize
chipping, cracking, particle generation, and damage to patterned device areas.
Mechanical Blade Dicing
Mechanical blade dicing uses a high-speed precision spindle fitted with a thin
diamond-embedded blade. The blade travels along predefined dicing streets to divide
the wafer into individual dies. It is one of the most widely used methods for
semiconductor dicing because it is repeatable, cost-effective, and
suitable for many standard silicon wafer thicknesses.
Blade type, spindle speed, feed rate, cooling-water flow, and cut depth must be
controlled carefully. Proper process selection helps reduce front-side and backside
chipping while maintaining the requested die-size tolerance. Mechanical sawing is
often appropriate for silicon coupons, sensor substrates, test pieces, and larger
rectangular dies.
Laser Wafer Dicing
Laser wafer dicing is a non-contact cutting method that uses a
focused laser to remove material or create a controlled separation path. Because
there is no physical blade contacting the wafer, laser dicing can reduce mechanical
loading and may be useful for thin wafers, narrow dicing streets, fragile devices,
or applications requiring complex die geometries.
Laser parameters such as wavelength, pulse duration, power, repetition rate, and
scanning speed affect kerf width, heat-affected zones, debris generation, and edge
quality. The optimal settings depend on wafer thickness, surface coatings,
metallization, dielectric layers, and the required final dimensions.
Scribe-and-Break Wafer Dicing
Scribe-and-break processing creates a controlled score line on the wafer surface and
then applies mechanical force to separate the wafer along the crystal plane. This
technique can reduce material loss because the scribe line may be narrower than the
kerf produced by a conventional dicing blade.
Scribing is especially dependent on crystal orientation, wafer thickness, surface
condition, and die geometry. It may be suitable for simple rectangular or square
silicon dies when clean, predictable fracture paths can be maintained.
Stealth Dicing and Thermal Laser Separation
Stealth dicing focuses laser energy below the wafer surface to create a modified
internal layer. The wafer is then expanded or separated along the weakened path.
Because the primary modification occurs inside the wafer, this method can produce a
narrow effective kerf and limit surface debris.
Thermal laser separation uses controlled heating and cooling to create and guide a
crack through the substrate. These processes can be considered when low particle
generation, narrow separation paths, or reduced mechanical contact are important.
Suitability depends on the wafer material, thickness, device layout, and allowable
thermal exposure.
Plasma Dicing
Plasma dicing, sometimes called dicing by deep reactive ion etching,
separates dies by etching through exposed dicing streets. Unlike blade dicing, plasma
processing does not rely on mechanical sawing and can support narrow streets,
non-rectangular die shapes, and high die density.
Plasma dicing may improve the number of usable dies obtained from a wafer, especially
for small devices where conventional saw streets consume valuable surface area.
However, the wafer normally requires a compatible masking process and suitable
front-end fabrication preparation.
How to Specify Custom Diced Silicon Wafers
To request a quote for custom diced silicon wafers, provide as many
of the following specifications as possible:
- Wafer material and diameter
- Wafer thickness and thickness tolerance
- Requested die length and width
- Die-size and edge tolerances
- Crystal orientation, such as <100> or <111>
- Conductivity type, dopant, and resistivity
- Single-side polished or double-side polished surface
- Coatings, oxide layers, metallization, or patterned features
- Required cleaning, tape mounting, packaging, or individual handling
- Quantity of full wafers or finished dies
For applications requiring extremely high resistivity, consider
undoped silicon wafers.
For devices that require polished front and back surfaces, review
double-side polished silicon wafers.
Wafers can also be prepared using
RCA cleaning
before dicing or packaging when cleaner surfaces are required.
Applications for Diced Silicon Wafers
Custom silicon dies and coupons are commonly used for:
- MEMS device fabrication
- Integrated circuits and microelectronic packaging
- Thin-film deposition and coating experiments
- Optical, photonic, and sensor development
- Surface analysis and spectroscopy
- Semiconductor process development
- University laboratory instruction
- Prototype fabrication and materials research
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